Rapid quantitative assays for glucose-6-phosphate dehydrogenase (G6PD) and hemoglobin combined on a capillary-driven microfluidic chip

Rapid tests for glucose-6-phosphate dehydrogenase (G6PD) are extremely important for determining G6PD deficiency, a widespread metabolic disorder which triggers hemolytic anemia in response to primaquine and tafenoquine medication, the most effective drugs for the radical cure of malaria caused by Plasmodium parasites. Current point-of-care diagnostic devices for G6PD are either qualitative, do not normalize G6PD activity to the hemoglobin concentration, or are very expensive. In this work we developed a capillary-driven microfluidic chip to perform a quantitative G6PD test and a hemoglobin measurement within 2 minutes and using less than 2 μL of sample. We used a powerful microfluidic module to integrate and resuspend locally the reagents needed for the G6PD assay and controls. We also developed a theoretical model that successfully predicts the enzymatic reactions on-chip, guides on-chip reagent spotting and allows efficient integration of multiple assays in miniaturized formats with only a few nanograms of reagents

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching of Pt/TiO2/Pt thin films are first characterized with resistance ratio up to 5 orders of magnitude. Then co-integration of Pt/TiO2/Pt or Pt/TiO2 memory cells on 140 um and 60 um diameter Cu TSV are fabricated. Repeatable non-volatile bipolar switching of the ReRAM cells are demonstrated for different structures

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3-D network-on-chip (NoC), which can route packets in the vertical direction. Superimposing identical planar dies minimizes design effort and manufacturing costs, ensuring at the same time high flexibility and reconfigurability. A single die can be used either as a fully testable standalone chip multi-processor (CMP), or integrated in a 3-D stack, increasing the overall core count and consequently the system performance. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90 nm complementary metal–oxide–semiconductor process and stacked using an in-house, via-last Cu-TSV process. Initial results show that the proposed 3-D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gb/s

A portable potentiometric electronic tongue leveraging smartphone and cloud platforms

Electronic tongues based on potentiometry offer the prospect of rapid and continuous chemical fingerprinting for portable and remote systems. The present contribution presents a technology platform including a miniaturized electronic tongue based on electropolymerized ion-sensitive films, microcontroller-based data acquisition, a smartphone interface and cloud computing back-end for data storage and deployment of machine learning models. The sensor array records a series of differential voltages without use of a true reference electrode and the resulting time-series potentiometry data is used to train supervised machine learning algorithms. For trained systems, inferencing tasks such as the classification of liquids are realized within less than 1 minute including data acquisition at the edge and inference using the cloud-deployed machine learning model. Preliminary demonstration of the complete electronic tongue technology stack is reported for the classification of beverages and mineral water.Comment: 2019 ISOCS/IEEE International Symposium on Olfaction and Electronic Nose (ISOEN

Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling

Abstract—New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation highperformance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs, supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility. Thus, both power and thermal/cooling implications play a major role in the design of new HPC systems, given the energy constraints in our society. Therefore, EPFL, IBM and ETHZ have been working within the CMOSAIC Nano-Tera.ch program project in the last three years on the development of a holistic thermally-aware design. This paper presents the exploration in CMOSAIC of novel cooling technologies, as well as suitable thermal modeling and system-level design methods, which are all necessary to develop 3D MPSoCs with inter-tier liquid cooling systems. As a result, we develop energy-efficient run-time thermal control strategies to achieve energy-efficient cooling mechanisms to compress almost 1 Tera nano sized functional units into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible. The proposed thermally-aware design paradigm includes exploring the synergies of hardware-, software- and mechanical-based thermal control techniques as a fundamental step to design 3D MPSoCs for HPC systems. More precisely, we target the use of inter-tier coolants ranging from liquid water and twophase refrigerants to novel engineered environmentally friendly nano-fluids, as well as using specifically designed micro-channel arrangements, in combination with the use of dynamic thermal management at system-level to tune the flow rate of the coolant in each micro-channel to achieve thermally-balanced 3D-ICs. Our management strategy prevents the system from surpassing the given threshold temperature while achieving up to 67% reduction in cooling energy and up to 30% reduction in system-level energy in comparison to setting the flow rate at the maximum value to handle the worst-case temperature

Inactivating KISS1 mutation and hypogonadotropic hypogonadism

Gonadotropin-releasing hormone (GnRH) is the central regulator of gonadotropins, which stimulate gonadal function. Hypothalamic neurons that produce kisspeptin and neurokinin B stimulate GnRH release. Inactivating mutations in the genes encoding the human kisspeptin receptor (KISS1R, formerly called GPR54), neurokinin B (TAC3), and the neurokinin B receptor (TACR3) result in pubertal failure. However, human kisspeptin loss-of-function mutations have not been described, and contradictory findings have been reported in Kiss1-knockout mice. We describe an inactivating mutation in KISS1 in a large consanguineous family that results in failure of pubertal progression, indicating that functional kisspeptin is important for puberty and reproduction in humans. (Funded by the Scientific and Technological Research Council of Turkey [TÜBİTAK] and others.)http://www.nejm.org/nf201

Post-cmos processing and 3d integration based on dry-film lithography

A method for performing a post processing pattern on a diced chip having a foot-print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern

Fabrication and characterization of wafer-level deep TSV arrays

Three Dimensional (3D) integration, based on through silicon vias (TSV), has the potential to become a key enabling technology for many applications. TSVs are commonly categorized according to their aspect ratio and diameter. An equally important parameter of the TSV, usually omitted, is their depth. This paper discusses the fabrication process, characterization and detailed failure analysis of deep Cu TSVs, with high aspect ratio. For the proposed process, TSVs are etched on a 380 mu m thick wafer using standard deep reactive ion etching (DRIE). The electroplating is performed in two steps, the first step seals off one side of the TSV using super conformal chemistry, Dow chemical Intervia (TM) 8520 bath, and the second step uses the now partially filled via as a seed layer for a bottom up technique, bath Intervia (TM) 8510 or Intervia (TM) 8520 Dow Chemical. After the electroplating, a chemical-mechanical polishing (CMP) step is used to planarize the wafer, and double-sided metal sputtering and photolithography are performed to connect the TSVs in a daisy chain. A conventional bonding technique, like solder bumps, can be used to bond layers with TSVs